Method of forming stable native oxide on gallium arsenide based compound semiconductors by combined drying and annealing

ABSTRACT

A method of forming a highly stable oxide on gallium arsenide containing compound semiconductors. A native oxide is grown on the surface of the semiconductor and dried during a suitable baking cycle. The oxide is then annealed at a temperature which is significantly higher than that of the baking cycle. This annealing step densifies the oxide and renders it particularly stable and impervious to impurities. In a particular embodiment, a diffusion mask is formed in accordance with the invention to permit selective area diffusion of impurities into a gallium arsenide containing compound semiconductor.

United States Patent 1 1 Schwartz et a1.

[ METHOD OF FORMING STABLE NATIVE OXIDE ON GALLIUM ARSENIDE BASED COMPOUND SEMICONDUCTORS BY COMBINED DRYING AND ANNEALING [75] Inventors: Bertram Schwartz, Westfield; Stuart Marshall Spitzer, Berkeley Heights; Gregory Dyett Weigle, Somerset, all of NJ.

[73] Assignee: Bell Telephone Laboratories,

Incorporated, Murray Hill, NJ.

[22] Filed: Mar. 26, 1973 [21] Appl. N0.: 344,702

[52] US. Cl. 148/187; 117/200; 156/17; 148/].5; 204/56 R [51] Int. Cl. H011 7/44 [58] Field of Search 148/187, 115, 138;

[56] References Cited UNITED STATES PATENTS 2,686,279 8/1954 Barton 204/56 R 3,531,383 9/1970 Lochmann et a] 204/56 R 3,660,178 5/1972 Takahashi et a1....... 148/187 3,687,745 8/1972 Chang et a1 148/187 1 1 June 17, 1975 3/1974 Schwartz 204/56 R Films; in Journ. Electrochem. Soc, 1971, pp. 1619-1923.

Primary Examiner-Walter R. Satterfield Attorney, Agent, or FirmL. H. Birnbaum [57] ABSTRACT A method of forming a highly stable oxide on gallium arsenide containing compound semiconductors. A native oxide is grown on the surface of the semiconductor and dried during a suitable baking cycle. The oxide is then annealed at a temperature which is significantly higher than that of the baking cycle. This annealing step densities the oxide and renders it particularly stable and impervious to impurities. In a particular embodiment, a diffusion mask is formed in accordance with the invention to permit selective area diffusion of impurities into a gallium arsenide containing compound semiconductor.

4 Claims, 6 Drawing Figures PATENTEII I I 7 I975 {WEN 1 .890.169

FIG.

ELECTROLYTICALLY GROW OXIDE ON SURFACE OF SEMICONDUCTOR DRY OXIDE BY HEATING To TEMPERATURE OF |50-300c FOR 1/2 HOUR To 5 HOURS FORM MASK PATTERN BY PHOTOLITHOGRAPHY ANNEAL OXIDE BY HEATING TO TEMPERATURE OF SOC-700C FOR I5 MINUTES TO 4 HOURS I DIFFUSE IMPURITIES INTO EXPOSED I PORTIONS OF SEMICONDUCTOR PATENTEDJUN 17 1915 Mt? 8 90,169

FIG. 28

FIG. 26

FIG-2E METHOD OF FORMING STABLE NATIVE OXIDE ON GALLIUM ARSENIDE BASED COMPOUND SEMICONDUCTORS BY COMBINED DRYING AND ANNEALING BACKGROUND OF THE INVENTION This invention relates to the fabrication of devices employing gallium arsenide containing compound semiconductors.

In one aspect. the invention relates to a process of forming a native oxide on such a compound semiconductor which is especially stable and impervious to impurities.

In another aspect, the invention relates to a process for the selective diffusion of impurities into such a corn pound semiconductor and more particularly to a method of forming a diffusion mask for the control of such diffusion.

With the growing importance of gallium arsenide compound semiconductors for such applications as light emitting devices, increasing importance has been placed on developing an economical planar processing technology for these materials. One of the important fields of concern is the ability to form a layer on the surface of the semiconductor which can be used for such applications as passivation and diffusion masking. In a selective area diffusion process in particular a mask is required which will be resistant to the dopants at high temperatures while adhering to the surface of the semiconductor. A further requirement is that the masking layer permit precise line definition of the diffused regions. Deposited insulators such as SiO or Si N suffer from the problem of lifting and cracking during high temperature diffusions since there is not a sufficient bond between the insulator and semiconductor material. Other deposited insulators such as phosphosilicate glass and aluminum oxide do not permit precise line definition when used as masks since considerable lateral diffusion is observed at the dielectricscmiconductor interface.

The recent discovery of a method for growing a native oxide on gallium arsenide compound semiconductors offered considerable promise in eliminating the insulator-semieonductor interface problems inherent in the use of deposited insulators. (See US. patent application of B. Schwartz, Ser. No. 292,127, filed Sept. 25, I972 and assigned to the present assignee, now US. Pat. No. 3,798,I39.) However, it was discovered that the native oxide as grown tended to react with dopants such as Zn at the high temperatures required for diffusion, effectively destroying the oxide layer.

It is therefore an object of the invention to permit fabrication of devices from gallium arsenide containing compounds by the formation of a stable layer on the surface which will adhere strongly to the surface of the semiconductor and remain resistant to impurities even at high temperatures.

SUMMARY OF THE INVENTION This and other objects are achieved in accordance with the invention. A native oxide is first grown on the surface of the semiconductor and dried, according to known techniques. The oxide is then annealed at a higher temperature than that of the drying cycle. this anneal is found to stabilize the oxide and make it especially resistant to outside impurities and dopants normally employed in diffusion processes. In a particular embodiment involving selective area diffusion in a GaAs semiconductor, an oxide was grown electrolytically on the surface and the oxide dried at a temperature of approximately 250C for approximately 2 hours. The masking pattern was then delineated by standard photolithographic techniques. The oxide was then annealed at a temperature of approximately 600C for 30 minutes so as to be made resistant to a subsequent diffusion of Zn impurities into the exposed portion of the semiconductor.

BRIEF DESCRIPTION OF THE DRAWING These and other features of the invention will be delineated in detail in the description to follow. In the drawing:

FIG. 1 is a flow diagram showing the steps of one embodiment of the invention; and

FIGS. 2A -2E are cross-sectional views of a semiconductor sample in various stages of manufacture in accordance with the same embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION A method in accordance with one embodiment of the invention is illustrated in the flow diagram of FIG. 1 and in the cross-sectional view of a semiconductor device in various stages of manufacture shown in FIGS. 2A-2E.

The sample used in this particular example was a Sedoped, n-type GaAs wafer with (III) orientation and carrier concentration of i0"-10" cnr'. After standard polishing and degreasing of the wafer (10 of FIG. 2A), a native oxide, 1], was grown on the surface. The oxide was formed by making the wafer the anode in an electrolytic system employing as the electrolyte a 30% H 0 aqueous solution with a pH adjusted to 2 by H PO A constant voltage of about volts was applied to the system and the oxidation was performed at room temperature. An oxide thickness of approximately 1700 A was obtained after 5 minutes. As is known in the art, a useful range for the applied potential is approximately 5-l75 volts. A constant current source may be used in place of a constant voltage source. In addition, the oxidation may be performed at the boiling point of the electrolyte to further enhance oxide growth. It is also known that water alone may serve as the electrolyte. (For a detailed discussion of the electrolytic oxidation system, see US. Pat. application of B. Schwartz. Ser. No. 292,l27. filed Sept. 25, i972 and assigned to the present assignee, now US. Pat. No. 3,798,139.) It is further known that the oxide may be formed in chemical systems utilizing H O or H O alone as the oxidant (see US. Pat. application of R. L. Hartman, M. Kuhn and B. Schwartz, Ser. No. 239,708, filed Mar. 30, 1972). As illustrated in FIG. I the oxide was then dried. In this particular example. the sample was baked in a nitrogen ambient for 2 hours at 250C. In general, a drying cycle in the range of l5030()C for /2 hour to 5 hours in any dry nonoxidizing ambient would be useful.

Next, the oxide mask pattern was formed by standard photolithographic techniques. Generally. as shown in FIG. 23, this involves forming a photoresist. 12, over the oxide layer, exposing the photoresist to light through a suitable mask, and developing the photoresist so that the unexposed portion is etched away leav ing a window in the photoresist as shown in FIG. 2C. With the remaining photoresist serving as a mask, the

oxide may then be etched, for example, with aqueous HCl solution, to open a diffusion window in the oxide. The photoresist may then be stripped off with acetone leaving the oxide masking pattern on the surface of the substrate.

The oxide mask so formed will not stand up satisfactorily to the high temperature normally preferred for a Zn diffusion. We have found however, that high temperature stability can be achieved by annealing the oxide at a sufficiently high temperature to stabilize the oxide. In this particular example, the oxide was annealed at 600C for 30 minutes in dry nitrogen. This step serves to densify the oxide as evidenced by a decrease in thickness of approximately 50%. This is shown in FIG. 2D. Further experiments indicate a preferable range of values for annealing at 500700C for minutes to 4 hours. Useful annealing may be achieved with temperatures of 450700C for l5 minutes to 12 hours. Normally the longer the time and the higher the temperature the greater is the densifying. Any dry nonoxidizing ambient may be used in place of nitrogen. It should be noted that although in this example the anneal was performed subsequent to the formation of the mask pattern, the anneal may be performed prior to any mask definition if desired. The anneal preferably should be done after the drying step, however, otherwise the oxide may crack as the result of a too rapid escape of water from the oxide layer.

The desired dopant. in this case Zn, was then diffused into the exposed portion of the semiconductor to produce a p-type region 13 as shown in FIG. 2E. In accon dance with known techniques, the sample was placed in a closed system with powdered Zn As and GaAs which provided the Zn dopant and a partial pressure of As over the sample. The sample was heated at about 610C for 25 minutes to obtain a sheet resistivity of 4S Q/D and to diffuse the Zn impurities to a depth of approximately 3300 A. The oxide was visibly unchanged after the diffusion step. Subsequent experiments on other samples showed that the oxide would remain unchanged even after diffusion at 650C for times up to 2 hours.

As alluded to above, several other samples of GaAs were subjected to the steps of the present invention to produce masks of varying thickness. Some of the results are summarized in the following table:

purities occur within resolvable limits, indicating a high bond strength and low defect density at the interface between the oxide and semiconductor. Even in cases where the oxide did not completely mask against the dopant (e.g., oxide thickness of 800A), sharp boundaries were observed between the diffus n under the oxide and in the exposed portion of the semiconductor. It will be recognized that oxides of thickness less than 1300A may be used as diffusion buffers to prevent semiconductor surface damage. Thus, for example, in FIGS. 2D-2E, a thin oxide may be left in the etched window to protect the GaAs surface from damage and contamination from the ambient, while the thick portion of oxide defines the boundaries of the diffused regions. It is understood that the term diffusion mask" as used in this application and as generally understood by those skilled in the art refers to a layer which attenuates as well as blocks essentially completely the diffusion of impurities into the semiconductor.

While the invention has been described primarily in terms of the diffusion of Zn into GaAs semiconductors, it should be clear that the process contemplates other dopants and other semiconductor materials. For example, any dopant which can be diffused at temperatures within the annealing range described above should be included. These include phosphorous, selenium and tin. It is also expected that any substituted GaAs compound semiconductor will form essentially the same native oxide which will provide an effective diffusion mask after the annealing step in accordance with the invention. This oxide has been shown to be primarily a mixture of 621 0 and As O It is expected that the materials which may utilize the method of the invention can be generally described as Ga,.,X,Y As, where X may be Al or In, Y may be P or Sb, and, x and y may vary from zero to 0.95 (i.e., at least 5% of gallium arsenide should be present in the compound to form the oxide). Of special interest in this class are GaAlAs and GaPAs.

It should also be recognized that although the description of the invention has focused upon a selective area diffusion process, the formation of this stable oxide has many other uses. For example; the oxide may be used as a passivation layer to protect the semicon- Temperature Thickness Thickness Zn Depth Applied of of Oxide Annealing of Oxide Diffusion in Exposed Under Sample Potential Electrolyte As Grown Cycle After Anneal Cycle GaAs Oxide l l00\ Room Temp. |700A 650C 800A 6l0C- 0.85pm 0.55;.tm

15 Min 120 Min 2 150V Room Temp. 2880A 600C- lbOUA 610C- 0.35pm 0 30 Min 25 Min 3 100V Boiling 237 5A 600C- 1300A 6 l(lC- 0. 3 3pm 0 30 Min 25 Min 4 l V Boiling 4875A 600C- 3600A 620C- 0.44pm 0 30 Min 25 Min All samples were oxidized in an H 0 aqueous electr0- lyte for 5 minutes, the oxide dried at 250C for 2 hours in a nitrogen ambient and then a 0.34 mm wide stripe defined in the oxide. Annealing was also done in a nitrogen ambient.

It was discovered that a minimum oxide thickness of approximately l300A after the annealing cycle was required to completely mask against a 3300A Zn diffusion. It was observed that no lateral diffusion of Zn imductor material in the final device from outside contaminants. In another example, the oxide layer may be used as a mask in a selective etching process where it is desired to use an etchant such as aqua regia which would tend to dissolve the oxide as grown.

Various additional modifications and extensions of the invention will become apparent to those skilled in the art. All such variations which basically rely on the teachings through which the invention has advanced healing the oxide by heating to a temperature of approximately 450-700C for a period of approximately 15 minutes to 12 hours in a nonoxidizing ambient.

2. The method according to claim 1 wherein the oxide is annealed by heating to a temperature of approximately 500-700C for a period of approximately 15 minutes to 4 hours.

3. The method according to claim 1 wherein the nonoxidizing ambient is nitrogen.

4. The method according to claim 1 wherein the compound semiconductor is GaAs. 

1. IN A PROCESS FOR FABRICING A COMPOUND SEMICONDUCTOR DEVICE, THE METHOD OF FORMING A STABLE OXIDE ON THE SURFACE OF A SEMICONDUCTOR PORTION COMPRISNG A MATERIAL SELECTED FROM THE GROUP CONSISTING OF GASA, GAAIAS AND GAPAS, COMPRISING THE STEPS OF GROWING AN OXIDE ON THE SURFACE OF THE SAID SEMCONDUCTOR PORTION, DRYING SAID OXIDE BY HEATING TO A TEMPERTURE OOF APPROXIMATELY 150-300*C FOR APPROXIMATELY 1/2 HOUR TO 5 HOURS IN A NONOXIDIZING AMBEINT AND SUBSQUENTLY ANNEALING THE OXIDE BY HEATING TO A TEMPERATURE OF APPROXIMATELY 450*-700* FOR APERIOD OF APPROXIMATELY 15 MINUTES TO 12 HOURS IN A NONOXIDIZING AMBIENT.
 2. The method according to claim 1 wherein the oxide is annealed by heating to a temperature of approximately 500*-700*C for a period of approximately 15 minutes to 4 hours.
 3. The method according to claim 1 wherein the nonoxidizing ambient is nitrogen.
 4. The method according to claim 1 wherein the compound semiconductor is GaAs. 